The present invention relates to a semiconductor device having a semiconductor mounted structure in which a first LSI chip and a second LSI chip, each having LSI on the main surface, are bonded together with the main surfaces facing each other, and a method for manufacturing the same.
In order to realize a low cost and a small size of a semiconductor integrated circuit device, a COC (Chip On Chip)-structured semiconductor device in which a semiconductor mounted structure is formed by bonding two LSI chips by a face-down bonding method has been proposed. In each LSI chip, for example, LSI having a different function or LSI made by a different process is formed. An example of such a semiconductor device will be explained with reference to FIG. 8.
In the semiconductor device shown in FIG. 8, a first LSI chip 101 and a second LSI chip 104 are mounted. On the main surface of the first LSI chip 101 on which LSI (not shown) is formed, an internal electrode 102 and an external electrode 103 are formed. On the main surface of the second LSI chip 104 on which LSI (not shown) is formed, a bump 105 is formed. The first LSI chip 101 and the second LSI chip 104 are bonded together by a face-down bonding method in a state in which the internal electrode 102 is connected to the bump 105. Between the first LSI chip 101 and the second LSI chip 104, an insulating resin 106 is filled. The first LSI chip 101 is fixed to a die pad 107 of a lead frame by soldering. The external electrode 103 of the first LSI chip 101 is electrically connected to an inner lead 108 of the lead frame with a bonding wire 109 made of a metal fine wire. The first LSI chip 101, the second LSI chip 104, the die pad 107, the inner lead 108 and the bonding wire 109 are sealed with a sealing resin 110.
The above-mentioned semiconductor device is manufactured as follows. First, an insulating resin 106 is coated on the central portion of the first LSI chip 101, having the external electrodes 103 formed on the peripheral portions. Next, the second LSI chip 104 is pressed to the first LSI chip 101, and the first LSI chip 101 and the second LSI chip 104 are bonded together in a state in which the internal electrode 102 is connected to the bump 105.
Next, the external electrode 103 of the first LSI chip 101 is connected to the inner lead 108 of the lead frame with a bonding wire 109. Next, the first LSI chip 101, the second LSI chip 104, the die pad 107, the inner lead 108 and the bonding wire 109 are sealed with the sealing resin 110. Finally, an outer lead 111 of the lead frame, which protrudes from the sealing resin 110, is shaped. Thus, a semiconductor device is completed.
However, in the configuration of the above-mentioned semiconductor device, when the outside dimension of the second LSI chip 104 is larger than that of the first LSI chip 101 located at the lower side, there may arise a structural limitation in fabricating a semiconductor device by mounting on the lead frame. In particular, it becomes difficult to connect the external electrode 103 of the first LSI chip 101 to the inner lead 108 of the lead frame with the bonding wire 109.
For example, in the case where a memory chip is used for the second LSI chip 104 located at the upper side, with increases in the capacity of the memory chip in the future, the outside dimension of the chip also is increased. On the other hand, in the case where a logic chip is used for the first LSI chip 101 located at the lower side, as the processing becomes finer, the outside dimension of the chip is reduced. Consequently, the outside dimension of the memory chip becomes larger than that of the logic chip. In such a case, the above-mentioned problem becomes significant in the high-density semiconductor mounting technique.
In the meanwhile, JP 10(1998)-256472 A discloses a semiconductor device having a structure shown in FIG. 9. A second LSI chip 104a has the same outside dimension as that of a first LSI chip 101a located at the lower side. The chips are bonded together while rotated at an angle of 45xc2x0 relative to each other. Therefore, corner portions 112 and 113 of the both chips, which are shown in a hatch pattern, are exposed without overlapping. By providing these corner portions 112 and 113 with external electrodes (not shown), wiring is made possible regardless of the increase in the outside dimension of the second LSI chip 104.
However, in the wiring using such corner portions 112 and 113, since the number of the usable external electrodes extremely is limited, it is difficult to carry out satisfactory electrical connection. The reason is that with the mutual rotation of the chips, the exposed area is small. Furthermore, when considering that the insulating resin filled between the chips may protrude from the edge of the chip to form a so-called fillet, the margin of usable exposed area becomes further reduced.
With the foregoing in mind, it is an object of the present invention to provide a semiconductor device capable of effectively connecting between the semiconductor chip and the lead frame even in a COC structure in which the outside dimension of the semiconductor chip located at the upper side is larger than that of the semiconductor chip located at the lower side, and a method for manufacturing the same.
The semiconductor device of the present invention includes a lead frame having a die pad and leads provided in the vicinity of the die pad, a first semiconductor chip having first internal electrodes and first external electrodes on a surface thereof and mounted on the die pad, a second semiconductor chip having second internal electrodes and second external electrodes on a surface thereof and bonded to the first semiconductor chip with the surfaces facing each other, the second internal electrodes being connected to the respective first internal electrodes with bumps, first metal fine wires for connecting the leads to the respective first external electrodes and second metal fine wires for connecting the leads to the respective second external electrodes, and a sealing resin for sealing the leads, the first and second semiconductor chips and the first and second metal fine wires. The first semiconductor chip is superimposed onto the second semiconductor chip with the edges being shifted from each other while the edges are in parallel to each other, whereby a part of the end portions of the first and second semiconductor chip protrude from the edge of the counterpart semiconductor chips and the first and the second external electrodes are located in the protruded regions respectively.
With such a configuration, since the external electrodes are exposed without overlapping, the leads of the lead frame can be connected to the external electrodes with the metal fine wires without problems. It is noted that the condition of the edges being substantially in parallel may include the state such that the edges cross each other at an angle within an alignment accuracy in the COC mounting process. Specifically, if the angle between the edges is within xc2x11 degree, a practically sufficient effect can be achieved.
Furthermore, the semiconductor device may have a configuration in which a pair of opposite end portions of the first semiconductor chip protrude from the edge of the second semiconductor chip, and a pair of opposite end portions of the second semiconductor chip protrude from the edge of the first semiconductor chip. With such a configuration, it is possible to laminate a memory element that is a rectangular-shaped chip in most cases and a system LSI, etc. easily and simply. Note here that since the memory element has a structure in which electrode pads are disposed on both end portions in two sides in most cases, the existing memory elements easily can be used.
Alternatively, the semiconductor device may have a configuration in which one end portion of the first semiconductor chip protrudes from the edge of the second semiconductor chip and three end portions of the second semiconductor chip protrude from the edge of the first semiconductor chip. With such a configuration, it is possible to connect the first semiconductor chip and the second semiconductor chip partially via the bump in order to make shortest the electrical path between the first semiconductor chip 4 and the second semiconductor chip.
Alternatively, the semiconductor device may have a configuration in which the first semiconductor chip and the second semiconductor chip are arranged so as to be shifted from each other substantially in the diagonal direction and thereby two adjoining end portions of the first semiconductor chip and two adjoining end portions of the second semiconductor chips protrude from the edge of the chips. With such a configuration, it is possible to laminate square shaped chips easily and simply.
In the configuration, in the above-mentioned configuration, it is preferable that an insulating resin is filled in a gap between the first semiconductor chip and the second semiconductor chip, the end of the insulating resin is projected outward from the end of the first semiconductor chip or the second semiconductor chip to form a fillet, and the first and second external electrodes are located outside of the end of the fillet. Thus, it is possible to use the areas of the first and second electrodes effectively.
In order to do so, the semiconductor device may have a configuration in which in the portion where the first semiconductor chip/the second semiconductor chip protrudes, the total thickness t of the thickness of the first semiconductor chip/the second semiconductor chip and the thickness of the insulating resin, and the distance L between the edge of the second semiconductor chip/the first semiconductor chip and the inside edge of the first external electrode/the second external electrode satisfy the relationship: t less than L.
Practically, it is preferable that the distance between the protruding end of the second semiconductor chip/the first semiconductor chip and the edge of the first semiconductor chip/the second semiconductor chip is in the range from 0.3 mm to 2.0 mm.
The semiconductor device may have a configuration in which the first semiconductor chip is a logic chip or an analog chip and the second semiconductor chip is a memory chip having a larger outside dimension than the outside dimension of the first semiconductor chip. In this case, the semiconductor device may have a configuration in which the second semiconductor chip has at least one side longer than the side of the first semiconductor chip.
According to the method for manufacturing a semiconductor device of the present invention, onto a first semiconductor chip having first internal electrodes and first external electrodes on a main surface thereof, a second semiconductor chip having second internal electrodes and a second external electrodes on a main surface thereof is superimposed with the main surfaces facing each other to form a semiconductor mounted structure, the chips are bonded together, and the semiconductor mounted structure is mounted on a lead frame. This method includes forming the semiconductor mounted structure by superimposing the first semiconductor chip onto the second semiconductor chip with the edges being shifted from each other, while the edges are substantially in parallel to each other, whereby a part of the end portions of the first and the second semiconductor chips protrude from the edge of the counterpart semiconductor chip, and the first and the second external electrodes are located at the protruded regions respectively, and connecting the first internal electrodes to the respective second internal electrodes with bumps, mounting and adhering the semiconductor mounted structure on the lead frame having a die pad and leads provided in the vicinity of the die pad with the first semiconductor chip contacting with the surface of the die pad, connecting the first and second external electrodes to the respective leads with the first and the second metal fine wires respectively, and sealing a part of the lead of the lead frame, the semiconductor mounted structure, the first metal fine wires and the second metal fine wires with a sealing resin.
According to this manufacturing method, an external electrode of each semiconductor chip can be connected effectively to a lead with a metal fine wire.